Course description

FPGA for Electronics Engineers – Core 1: KiCad + Verilog + Vivado

This course provides a structured, practical introduction to FPGA development for electronics engineers, taking you from PCB design fundamentals all the way to the generation of an FPGA bitstream.

You will begin with KiCad PCB design, learning how to create schematics, work with component libraries and custom symbols, develop PCB layouts, assign footprints, perform Design Rule Checks (DRC), and generate Gerber files. The course then moves into digital logic foundations, covering number systems, binary and hexadecimal representation, two's complement, Boolean algebra, logic gates, combinational circuits, sequential logic, flip-flops, registers, and finite state machines.

The next section introduces Verilog HDL, including module structure, data types, ports, combinational and sequential logic, finite state machines, testbenches, waveforms, and a complete UART transmitter project.

Finally, you will work with AMD/Xilinx Vivado Design Suite, learning project creation, source management, synthesis, implementation, timing analysis, XDC constraints, and bitstream generation. XDC constraints are used to map Verilog ports to FPGA package pins and define timing requirements.

The course concludes with bitstream generation and report analysis, including utilisation, timing, DRC, power, clock interaction, and methodology reports. You will learn how to interpret the critical path and understand whether your design meets timing requirements.  



 

What will i learn?

  • Understand FPGA fundamentals
  • Design PCB schematics using KiCad
  • Create PCB layouts
  • Perform PCB validation
  • Build strong digital logic fundamentals
  • Learn Verilog HDL

Requirements

  • A computer/laptop capable of running the required software.
  • No physical FPGA development board is required for Core 1.
  • Internet access may be needed for downloading and installing the required software.
  • KiCad — for schematic and PCB design.
  • AMD/Xilinx Vivado Design Suite — for Verilog development, simulation, synthesis, implementation, timing analysis, XDC constraints, and bitstream generation.

Frequently asked question

This course teaches the FPGA development workflow using KiCad, Verilog HDL, and Vivado, from PCB design through bitstream generation.

No. Core 1 is specifically designed to be completed without physical hardware.

The course focuses on KiCad for PCB design and Vivado for FPGA design, synthesis, implementation, timing analysis, constraints, and bitstream generation.

No. The course includes an introductory Verilog section covering modules, ports, data types, combinational logic, sequential logic, FSMs, testbenches, and simulation.

XDC stands for Xilinx Design Constraints. It defines physical constraints such as FPGA pin assignments and timing constraints such as clock frequency.

John's Learnings

£7

Lectures

0

Skill level

Beginner

Expiry period

Lifetime

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